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| White Electronic Designs WV3HG32M40SEU-PD4 ADVANCED* 128MB - 32Mx40 DDR2 SDRAM UNBUFFERED, ECC, w/PLL FEATURES Unbuffered 200-pin, Small-Outline DIMM (SODIMM) Suppot ECC error detection and correction Fast data transfer rates: PC2-5300*, PC2-4200 and PC2-3200 Utilizes 667*, 533 and 400 Mb/s DDR2 SDRAM components VCC = 1.8V 0.1V VCCSPD = 1.7V to 3.6V JEDEC standard 1.8V I/O (SSTL_18-compatible) Differential data strobe (DQS, DQS#) option Differential clock inputs (CK, CK#) Four-bit prefetch architecture Programmable CAS# latency (CL): 3, 4, and 5 Posted CAS# additive latency; 0, 1, 2, 3 and 4 Programmable burst: length (4, 8) On-die termination (ODT) On memory PLL clock Serial Presence Detect (SPD) with EEPROM Auto & self refresh (64ms: 8,192 cycle refresh) Gold edge contacts RoHS Compliant JEDEC proposed Pin-out Package option: * 200 Pin (SO-DIMM) * PCB - 30.00mm (1.181") TYP. NOTE: Consult factory for availability of: * Vendor source control options * Industrial temperature option DESCRIPTION The WV3HG32M40SEU is a 32Mx40 Double Data Rate 2 SDRAM memory module based on 512Mb DDR2 SDRAM components. The module consists of three 32Mx16, in FBGA package mounted on a 200 pin SO-DIMM FR4 substrate. * This product is under development, is not qualified or characterized and is subject to change or cancellation without notice. OPERATING FREQUENCIES PC2-5300* Clock Speed CL-tRCD-tRP Note: * Consult factory for availability PC2-4200 266MHz 4-4-4 PC2-3200 200MHz 3-3-3 333MHz 5-5-5 June 2006 Rev. 2 1 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs PIN CONFIGURATION Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Symbol VREF VSS DQ0 DQ4 VSS DQ5 DQ1 VSS DQS0# DM0 DQS0 VSS VSS DQ6 DQ2 DQ7 DQ3 VSS VSS DQ12 DQ8 DQ13 DQ9 VSS VSS DM1 DQS1# VSS DQS1 DQ14 VSS DQ15 DQ10 VSS DQ11 DQ20 VSS DQ21 DQ16 VSS DQ17 NC VSS DM2 DQS2# VSS DQS2 DQ22 VSS DQ23 Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Symbol DQ18 VSS DQ19 DQ28 VSS DQ29 DQ24 VSS DQ25 DM3 VSS VSS DQS3# DQ30 DQS3 DQ31 VSS VSS DQ26 CB4 DQ27 CB5 VSS VSS CB0 DM8 CB1 VSS VSS CB6 DQS8# CB7 DQS8 VSS VSS CB2 CKE0 CB3 NC VSS NC NC VCC NC A12 A11 A9 VCC A7 A8 Pin No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 Symbol VCC A6 A5 A4 A3 VCC A2 A1 VCC A0 A10/AP BA1 BA0 VCC RAS# WE# VCC CS0# CAS# ODT0 NC NC VCC VCC NC CK NC CK# NC VSS VSS NC NC NC NC VSS NC NC VSS VSS NC NC NC NC VSS VSS NC NC NC NC Pin No. 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 Symbol VSS VSS NC NC NC VSS VSS NC NC NC NC VSS VSS NC NC NC NC VSS VSS NC NC VSS NC NC VSS NC NC VSS NC NC VSS NC NC VSS NC NC VSS NC NC VSS NC NC NC SDA VSS SCL NC SA1 VCCSPD SA0 WV3HG32M40SEU-PD4 ADVANCED PIN NAMES SYMBOL A0-A12 ODT0 CK, CK# CB0 - CB7 CKE0 CS0# RAS#, CAS#, WE# BA0, BA1 DM0-DM3, DM8 DQ0-DQ31 DQS0-DQS3, DQS8 DQS03-DQS3#, DQS8# SCL SA0-SA1 SDA VCC VREF VSS VCCSPD NC DESCRIPTION Address input On-Die Termination Clock Input Check Bits Clock Enable input Chip select Command Inputs Bank Address Inputs Input Data Mask Data Input/Output Data Strobe Data Strobe Complement SPD Clock Input SPD Address Inputs Serial Data Input/Output Power Supply Input/Output reference voltage Ground Serial EEPROM Power Supply No Connect June 2006 Rev. 2 2 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WV3HG32M40SEU-PD4 ADVANCED FUNCTIONAL BLOCK DIAGRAM CS0# DQS0 DQS0# DM0 CS DQS DQS# DM/RDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS# DM/RDQS I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 DQS1 DQS1# DM1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DQS2# DM2 DQS3 DQS3# DM3 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS DQS# DM/RDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS# DM/RDQS I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 CS DQS8 DQS8# DM8 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 CS DQS DQS# DM/RDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS# DM/RDQS I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 CK CK# P L L PCK0-PCK2 CK: DDR2 SDRAMs PCK0# PCK2# CK#: DDR2 SDRAMs CS0# BA0-BA1 A0-A12 RAS# CAS# WE# CKE0 ODT0 CS0# CS#: DDR2 SDRAMs BA0-BA1 BA0-BA1: DDR2 SDRAMs A0-A12 A0-A12: DDR2 SDRAMs RAS# RAS#: DDR2 SDRAMs CAS# CAS#: DDR2 SDRAMs WE# WE#: DDR2 SDRAMs CKE0 CKE: DDR2 SDRAMs ODT0 ODT: DDR2 SDRAMs SCL Serial PD WP A0 A1 A2 SA0 SA1 SDA VCCSPD VCC VREF Serial PD DDR2 SDRAMs DDR2 SDRAMs DDR2 SDRAMs NOTE: All resistor value, are 22 ohms 5% unless otherwise specified. VSS June 2006 Rev. 2 3 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs Symbol VCC VIN, VOUT TSTG Parameter Voltage on VCC pin relative to VSS Voltage on any pin relative to VSS Storage Temperature WV3HG32M40SEU-PD4 ADVANCED ABSOLUTE MAXIMUM RATINGS Min -0.5 -0.5 -55 Command/Address, RAS#, CAS#, WE# IL Input leakage current; Any input 0V DC OPERATING CONDITIONS All voltages referenced to VSS Rating Parameter Supply Voltage I/O Reference Voltage I/O Termination Voltage SPD Supply Voltage Symbol VCC VREF VTT VCCSPD Min. 1.7 0.49 x VCC VREF-0.04 1.7 Type 1.8 0.50 x VCC VREF - Max. 1.9 0.51 x VCC VREF+0.04 3.6 Units V V V V Notes 3 1 2 Notes: 1. VREF is expected to equal VCC/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +/-1 percent of the DC value. Peak-to-peak AC noise on VREF may not exceed +/-2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor. 2. VTT in sot applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 3. VCCQ of all IC's are tied to VCC. June 2006 Rev. 2 4 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs TA = 25C, f = 100MHz Parameter Input Capacitance (A0~A12, BA0~BA1, RAS#, CAS#, WE#) Input Capacitance CKE0, ODT0 Input Capacitance CS0# Input Capacitance (CK, CK#) Input Capacitance (DM0 ~ DM3, DM8), (DQS0 ~ DQS3, DQS8) Input Capacitance (DQ0 ~ DQ31) (CB0 ~ CB7) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 (665) CIN5 (534) COUT1 (665) COUT1 (534) WV3HG32M40SEU-PD4 ADVANCED INPUT/OUTPUT CAPACITANCE Min 7 7 7 6 6.5 6.5 6.5 6.5 Max 10 10 10 7 7.5 8 7.5 8 Units pF pF pF pF pF pF pF pF OPERATING TEMPERATURE CONDITION Parameter Operating temperature (Commercial) Symbol TOPER Rating 0 to 85 Units C Notes 1, 2 Notes: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDED JESD51.2 2. At 0C - 85C, operation temperature range, all DRAM specification will be supported. INPUT DC LOGIC LEVEL All voltages referenced to VSS Parameter Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Symbol VIH(DC) VIL(DC) Min VREF + 0.125 -0.300 Max VCC + 0.300 VREF - 0.125 Units V V INPUT AC LOGIC LEVEL All voltages referenced to VSS Parameter Input High (Logic 1) Voltage DDR2-400 & DDR2-533 Input Low (Logic 1) Voltage DDR2-667 Input Low (Logic 0) Voltage DDR2-400 & DDR2-533 Input Low (Logic 0) Voltage DDR2-667 Symbol VIH(AC) VIH(AC) VIL(AC) VIL(AC) Min VREF + 0.250 VREF + 0.200 Max VREF - 0.250 VREF - 0.200 Units V V V V June 2006 Rev. 2 5 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs Symbol ICC0* Proposed Conditions WV3HG32M40SEU-PD4 ADVANCED DDR2 ICC SPECIFICATION AND CONDITIONS 665 660 534 630 403 615 Units mA Operating one bank active-precharge; tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating one bank active-read-precharge; IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W Precharge power-down current; All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current; All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are SWITCHING Active power-down current; All banks open; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Fast PDN Exit MRS(12) = 0 Slow PDN Exit MRS(12) = 1 ICC1* 720 690 675 mA ICC2P** 330 330 324 mA ICC2Q** 390 375 360 mA ICC2N** 405 405 360 390 390 360 375 330 360 mA mA mA ICC3P** ICC3N** Active standby current; All banks open; tCK = tCK(ICC), tRC = tRC(ICC, tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W Burst auto refresh current; tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING Normal 480 450 450 mA ICC4W* 990 885 780 mA ICC4R* 990 885 780 mA ICC5** 1,110 1,050 990 mA ICC6** ICC7* 18 18 18 mA Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING. 1,725 1,470 1,245 mA ICC specification is based on ELPIDA components. Other DRAM manufactures specification may be different. Note: *: Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P (CKE LOW) mode. **: Value calculated reflects all module ranks in this operating condition. June 2006 Rev. 2 6 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs AC CHARACTERISTICS PARAMETER Clock Cycle Time CK high-level width CK low-level width Half clock period Clock jitter DQ output access time from CK/CK# Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# DQ and DM input setup time relative to DQS DQ and DM input hold time relative to DQS DQ and DM input pulse width (for each input) Data hold skew factor DQ...DQS hold, DQS to first DQ to go nonvalid, per access Data valid output window (DVW) DQS input high pulse width DQS input low pulse width DQS output access time from CK/CK# DQS falling edge to CK rising ... setup time DQS falling edge from CK rising ... hold time DQS...DQ skew, DQS to last DQ valid, per group, per access DQS read preamble DQS read postamble DQS write preamble setup time DQS write preamble DQS write postamble Write command to first DQS latching transition Address and control input pulse width for each input Address and control input setup time Address and control input hold time Address and control input hold time WV3HG32M40SEU-PD4 ADVANCED AC TIMING PARAMETERS & SPECIFICATIONS 665 CL = 5 CL = 4 CL = 3 SYMBOL tCK (5) tCK (4) tCK (3) tCH tCL tHP tJIT tAC tHZ tLZ tDS tDH tDIPW tQHS tQH tDVW tDQSH tDQSL tDQSCK tDSS tDSH tDQSQ tRPRE tRPST tWPRES tWPRE tWPST tDQSS tIPW tIS tIH tCCD 534 MAX 8,000 8,000 8,000 0.55 0.55 MIN 3,750 5,000 0.45 0.45 MIN (tCH, tCL) -125 -500 tAC MIN 100 225 0.35 tHP - tQHS tQH - tDQSQ 0.35 0.35 -450 0.2 0.2 MAX 8,000 8,000 0.55 0.55 MIN 5,000 5,000 0.45 403 MAX 8,000 8,000 0.55 0.55 UNIT ps ps ps tCK tCK ps 125 +600 tAC MAX tAC MAX ps ps ps ps ps ps tCK ps ps ns tCK tCK ps tCK tCK ps tCK tCK ps tCK tCK tCK tCK ps ps tCK MIN 3,000 3,750 5,000 0.45 0.45 MIN (tCH, tCL) -125 -450 tAC MIN 100 175 0.35 tHP - tQHS tQH - tDQSQ 0.35 0.35 -400 0.2 0.2 125 +450 tAC MAX tAC MAX 125 +500 tAC MAX tAC MAX 0.45 MIN (tCH, tCL) -125 -600 tAC MIN 150 275 0.35 tHP - tQHS tQH - tDQSQ 0.35 0.35 -500 0.2 0.2 Data 340 400 450 +400 +450 +500 Data Strobe 240 0.9 0.4 0 0.35 0.4 WL - 0.25 0.6 200 275 2 300 0.9 0.4 0 0.35 0.4 WL - 0.25 0.6 250 375 2 350 0.9 0.4 0 0.35 0.4 WL - 0.25 0.6 350 475 2 1.1 0.6 1.1 0.6 1.1 0.6 0.6 WL + 0.25 0.6 WL + 0.25 0.6 WL + 0.25 Note: AC specification is based on ELPIDA components. Other DRAM manufactures specification may be different. Continued on next page June 2006 Rev. 2 7 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs AC CHARACTERISTICS PARAMETER ACTIVE to ACTIVE (same bank) command ACTIVE bank a to ACTIVE bank b command ACTIVE to READ or WRITE delay Four Bank Activate period ACTIVE to PRECHARGE command Internal READ to precharge command delay Write recovery time Auto precharge write recovery + precharge time Internal WRITE to READ command delay PRECHARGE command period PRECHARGE ALL command period LOAD MODE command cycle time CKE low to CK,CK# uncertainty REFRESH to Active of Refresh to Refresh command interfal WV3HG32M40SEU-PD4 ADVANCED AC TIMING PARAMETERS (cont'd) 665 SYMBOL tRC tRRD tRCD tFAW tRAS tRTP tWR tDAL tWTR tRP tRPA tMRD tDELAY tRFC tREFI tXSNR tXSRD tISXR tAOND tAON tAOFD tAOF tAONPD tRFC (MIN) + 10 200 tIS 2 tAC (MIN) 2.5 tAC (MIN) tAC (MIN) + 2000 tAC (MIN) + 2000 3 8 2 7 - AL 2 3 2 tAC (MAX) + 700 2.5 tAC (MAX) + 600 2 x tCK + tAC (MAX) + 1000 2.5 x tCK + tAC (MAX) + 1000 534 MAX MIN 55 10 15 50 45 7.5 15 tWR + tRP 7.5 15 tRP+tCK 2 tIS + tCK + tIH 105 403 MAX MIN 55 10 15 50 40 7.5 15 tWR + tRP 10 15 tRP+tCK 2 tIS + tCK + tIH 105 MIN 55 10 15 50 45 7.5 15 tWR + tRP 7.5 15 tRP+tCK 2 tIS + tCK + tIH 105 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns tCK ns ns s ns tCK ps Command and Address 70,000 70,000 70,000 70,000 7.8 70,000 7.8 70,000 7.8 Self Refresh Average periodic refresh interval Exit self refresh to non-READ command Exit self refresh to READ command Exit self refresh timing reference ODT turn-on delay ODT turn-on ODT turn-off delay ODT turn-off tRFC (MIN) + 10 200 tIS 2 tAC (MIN) 2.5 tAC (MIN) tAC (MIN) + 2000 tAC (MIN) + 2000 3 8 2 6 - AL 2 3 2 tAC (MAX) + 1000 2.5 tAC (MAX) + 600 2 x tCK + tAC (MAX) + 1000 2.5 x tCK + tAC (MAX) + 1000 tRFC (MIN) + 10 200 tIS 2 tAC (MIN) 2.5 tAC (MIN) tAC (MIN) + 2000 tAC (MIN) + 2000 3 8 2 6 - AL 2 3 2 tAC (MAX) + 1000 2.5 tAC (MAX) + 600 2 x tCK + tAC (MAX) + 1000 2.5 x tCK + tAC (MAX) + 1000 tCK ps tCK ps ps ODT ODT turn-on (power-down mode) ODT turn-off (power-down mode) ODT to power-down entry latency ODT power-down exit latency Exit active power-down to READ command, MR[bit12=0] Exit active power-down to READ command, MR[bit12=1] A Exit precharge power-down to any non-READ command. CKE minimum high/low time tAOFPD tANPD tAXPD tXARD tXARDS tXP tCKE ps tCK tCK tCK tCK tCK tCK Note: AC specification is based on ELPIDA components. Other DRAM manufactures specification may be different. June 2006 Rev. 2 Power-Down 8 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs Clock/Data Rate Frequency 333MHz/667Mb/s 266MHz/533Mb/s 200MHz/400Mb/s WV3HG32M40SEU-PD4 ADVANCED ORDERING INFORMATION FOR PD4 Part Number WV3HG32M40SEU665PD4xxG* WV3HG32M40SEU534PD4xxG WV3HG32M40SEU403PD4xxG * Consult Factory for availability NOTES: * RoHS product. ("G" = RoHS Compliant) * Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case "x" in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung, Elpida & consult factory for others) * Consult factory for availability of industrial temperature (-40C to 85C) option CAS Latency 5 4 3 tRCD 5 4 3 tRP 5 4 3 Height** 30.00mm (1.181") TYP 30.00mm (1.181") TYP 30.00mm (1.181") TYP PACKAGE DIMENSIONS FOR PD4 FRONT VIEW 67.75 (2.667) 67.45 (2.656) 3.302 (0.130) MAX 4.10(0.161) (2X) 3.90(0.154) 1.80 (0.071) (2X) 30.15 (1.187) 29.85 (1.175) 20.00 (0.787) TYP 6.00 (0.236) 2.55 (0.100) 2.15 (0.085) 1.10 (0.043) 0.90 (0.035) 1.00 (0.039) TYP PIN 1 0.45 (0.018) TYP 63.60 (2.504) TYP 0.60 (0.024) TYP PIN 199 BACK VIEW PIN 200 4.2 (0.165) TYP 47.40 (1.866) TYP 11.40 (0.449) TYP PIN 2 ** ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) June 2006 Rev. 2 9 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WV3HG32M40SEU-PD4 ADVANCED PART NUMBERING GUIDE WV 3 H G 32M 40 S E U xxx PD4 x x G WEDC MEMORY (SDRAM) DDR 2 GOLD DEPTH BUS WIDTH COMPONENT WIDTH x16 1.8V UNBUFFERED SPEED (Mb/s) PACKAGE 200 PIN (P = JEDEC proposed pin-out) INDUSTRIAL TEMP OPTION (For commercial leave "blank" for industrial add "I") COMPONENT VENDOR NAME (E = Elpida) G = RoHS COMPLIANT June 2006 Rev. 2 10 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs Document Title 128MB - 32Mx40 DDR2 SDRAM UNBUFFERED DRAM DIE OPTIONS: * ELPIDA: F-Die WV3HG32M40SEU-PD4 ADVANCED Rev # Rev 0 Rev 1 History Created 1.0 Update to x40 depth 1.1 Added CB4, CB5, CB6, and CB7 1.2 Indicated SPD supply voltage 1.3 Change part number to indicated x40 (8 ECC bits) Release Date 6-06 6-8-06 Status Concept Concept Rev 2 2.0 Moved from concept to advanced 6-9-06 Advanced June 2006 Rev. 2 11 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com |
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